1. Field of the Invention
The present invention relates to non-volatile memory devices and methods of manufacturing the same. More particularly, the present invention relates to gate structures, such as silicon oxide nitride oxide semiconductor (SONOS) structures or metal oxide nitride oxide semiconductor (MONOS) structures, of non-volatile memory devices and methods of manufacturing the same.
2. Description of the Related Art
A semiconductor device, in general, may be classified as a volatile semiconductor memory device or a non-volatile semiconductor memory device. Volatile semiconductor memory devices, such as dynamic random access memory (DRAM) devices and/or static random access memory (SRAM) devices, have a relatively high response speed. However, the volatile semiconductor memory devices may lose data stored therein when applied power is shut off. Although non-volatile semiconductor memory devices, such as electrically erasable programmable read only memory (EEPROM) devices and/or flash memory devices, have a relatively slow response speed, non-volatile semiconductor memory devices can maintain data stored therein when the applied power is shut off. In EEPROM devices, data may be electrically stored (i.e., programmed) or erased through a Fowler-Nordheim (F-N) tunneling mechanism and/or a channel hot electron injection mechanism. Flash memory devices may be classified into non-volatile memory devices of the type having a floating gate electrode and non-volatile memory devices of SONOS type or MONOS type.
For example, non-volatile memory devices including a tunnel oxide layer, a charge trapping layer, and a gate dielectric layer (or a blocking layer) are disclosed in U.S. Patent Application Publication No. 2004/0251489, Japanese Patent Application Publication No. 2004-158810 and Korean Patent Application Publication Nos. 2004-106074 and 2004-93606.
Recently, a high-k material layer having a relatively high dielectric constant (or permittivity) has been used as a gate dielectric layer. For example, a high-k material, such as aluminum oxide, hafnium oxide, zirconium oxide, and the like, has been used in the gate dielectric layer for improving the capacitance of a cell transistor.
According to U.S. Patent Application Publication No. 2004/0251489, a SONOS memory device includes a tunnel oxide layer, a memory node layer, a blocking layer, and an electrode layer. The blocking layer includes an aluminum oxide layer serving as a first blocking layer and a hafnium oxide layer or a zirconium oxide layer serving as a second blocking layer. When, the high-k material is used in the gate dielectric layer of the non-volatile memory device is of the SONOS type, a leakage current problem may occur due to crystallization of the gate dielectric layer.
In more detail, a gate structure is formed by patterning the tunnel oxide layer, the memory node layer, the blocking layer, and the electrode layer. Damage caused by the patterning process may be cured by performing a heat treatment process. The blocking layer of the gate structure is crystallized during the heat treatment. The crystallization of the blocking layer may cause current to leak through the blocking layer, which may deteriorate operating characteristics of the non-volatile memory device. The problem may be exacerbated when the high-k material is individually used in a single layered gate dielectric layer as the surface morphology of the gate dielectric layer may deteriorate and leakage current through the gate dielectric layer may increase.